By James J. Licari
This publication is exclusive in its entire assurance of all points of adhesive know-how for microelectronic units and packaging, from concept to bonding to check tactics. as well as basic functions, reminiscent of dies, substrate, and lid and chip stack attachments, the e-book comprises new advancements in anisotropic, electrically conductive, and underfill adhesives. swift curing tools reminiscent of UV, microwave, and moisture (which conform to present environmental and effort specifications) are lined. Over eighty tables and a hundred and twenty figures supply a wealth of information on houses, functionality, and reliability. additionally integrated are examples of commercially to be had adhesives, providers, and gear. every one bankruptcy offers complete references.
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Extra resources for Adhesives Technology for Electronic Applications: Materials, Processing, Reliability
1997) 23. Ngulty, T. , and Ekere, N. , Chip Scale vs Flip Chip: Issues to Consider, Circuits Assembly (Nov. 1999) 24. Schueller, R. , Portable CSP, Advanced Packaging (May 1998) 25. , pp. 91–94 (Feb. 2000) 26. , Advantages of System on a Package and System on a Chip, Electronic Packaging and Production (Jul. 2001) 27. /Aug. 1999) 28. /Jul. 2000) 29. , No Place To Go But Up, Electronic Packaging and Production (Oct. 2001) INTRODUCTION 37 30. Guidelines for Multichip Module Technology Utilization, IPC-MC-790, Institute of Interconnecting and Packaging Electronic Circuits, Lincolnwood, IL (Aug.
6) by considering the drop in pressure (p) across a liquid-vapor interface: Eq. 7) ∂p − 12 µ ∂L = ∂x h 2 ∂t where µ is viscosity of the underfill material, h is the gap height, and L is the length of the die surface traveled by the underfill. The equation is solved by separating the distance (x) and time (t) variables, resulting in: Eq. 8) Ã=− 2γ cos θ hL where γ is the surface tension of the liquid-vapor interface and Γ is a constant. Application of boundary conditions resulted in the time, tf , to reach a distance, L f, between the parallel plates, of: 3 ìL f 2 Eq.
Example of lead-on-chip (LOC) construction. 20 ADHESIVES T ECHNOLOGY FOR E LECTRONIC APPLICATIONS chip stacked on an static random-access memory (SRAM), the chips may be connected by wire bonding or flip-chip bonding, first to each other, then to a base substrate. Where the chips are of the same size, they must be staggered so that all the wire bond connections can be made from one side of each device to the base substrate. Cross sections of wire-bonded, twochip and three-chip stacks are shown in Fig.